Sigma-delta modulators (sometimes referred to as delta-sigma modulators) have been used in analog-to-digital converters (ADCs) for some time. The reader is referred to the following technical articles incorporated herein by reference.
1) "A Use of Limit Cycle Oscillators to Obtain Robust Analog to Digital Converters", J. C. Candy, IEEE TRANSACTIONS ON COMMUNICATIONS, Vol. COM-22, No. 3, pp. 298-305, March, 1974. PA0 2) "Using Triangularly Weighted Interpolation to Get 13-Bit PCM from a Sigma-Delta Modulator", J. C. Candy, et al., IEEE TRANSACTIONS ON COMMUNICATIONS, Vol. COM-24, No. 11, pp. 1268-1275, November, 1976. PA0 3) "A Use of Double Integration in Sigma Delta Modulation", J. C. Candy, IEEE TRANSACTIONS ON COMMUNICATIONS, Vol. COM-33, No. 3, pp. 249-258, March, 1985. PA0 4) "Bandpass Sigma-Delta Modulation", R. Schreier, et al., ELECTRONICS LETTERS, Vol. 25, No. 23, pp. 1560-1561, Nov. 9, 1989.
Substantial effort has been made by specialists in the field of oversampled converter design to develop plural-order sigma-delta modulators, so as to obtain higher resolution for a given oversampling ratio, R. Two approaches to designing higher-order sigma-delta modulators are known.
One approach to designing an N.sup.th -order sigma-delta modulator, where N is an integer greater than one, is to modify the loop of a first-order sigma-delta modulator so as include after the analog integrator at least one further analog integrator in a cascade connection of N analog integrators preceeding the digital-to-analog converter. Each further analog integrator is connected for generating an integrated response to the difference between the analog feedback signal and the integrated response of the one of said analog integrators preceding it in the cascade connection.
Such sampled-data sigma-delta converters filter the quantization noise spectrum with a system function H(z) that is simply differentiation by discrete time--i.e., H(z)=(1-z.sup.-1).sup.N. Customarily, sigma-delta converters provide what is referred to as "sinusoidal" shaping of quantization noise, wherein the quantization noise previous to shaping through multiplication by H(z) is assumed to be white--i.e., to exhibit a broad-band flat response. This allows the output noise spectrum to be approximated by EQU S.sub.N (.omega.T)=K.sub.QN [2 sin(.omega.T/2)].sup.2N ( 1)
where K.sub.QN is the power-spectral-density (PSD) of the unshaped quantization noise. The final noise, accompanying the response of the decimation filtering which follows the sigma-delta modulator, is determined by integrating S.sub.N (.omega.T) over the baseband--i.e., from .omega.=0 to .omega.=.pi./R. Using this noise level, the theoretically attainable resolution, B, of a sigma-delta converter with the customary sinusoidal noise shaping can be expressed in terms of bits as follows: EQU B=(L+0.5) log.sub.2 R-log.sub.2 [.pi..sup.N (2N+1).sup.-0.5 ]+log.sub.2 (2.sup.P -1). (2)
Resolution as so expressed increases by one bit per octave of oversampling for each integer increment in modulator order N.
The number of bits resolution obtained, B, to good approximation is linearly related to P, the number of quantizer bits used in the sigma-delta modulator. It is desirable, then, to be able to use multiple-bit quantization in the sigma-delta modulator, in order to increase overall resolution in the oversampling converter. However, the accuracy of the digital-to-analog converter (DAC) in the quantizer must be consistent with the linearity required of the oversampled ADC after decimation, or else resolution is limited to less than that theoretically attainable. In high-resolution ADCs, this can be a formidable limitation. For example, a 16-bit sigma-delta ADC using a 4-bit quantizer requires 16-bit accuracy from the DAC within the quantizer. Obtaining such accuracy from a DAC is difficult, even with trimming, so it is desirable to avoid this costly requirement.
To avoid the problems of nonlinearity in the DACs, the common practice is to use single-bit DACs after single-bit quantizers, or ADCs, in sigma-delta modulators. In such configurations errors in the two levels of DAC output can introduce gain errors or offset errors, or both. However, the linearity of the converter is never compromised, since a straight line invariably will fit through just two points.
Another approach to designing an N.sup.th -order sigma-delta modulator, described by R. Schreier, et al. in their paper "Bandpass Sigma-Delta Modulation", uses a second-order resonator or cascade of them in a single feedback loop. Each resonator consists of two cascaded integrators with feedback applied from output to input, which increases the order of the sigma-delta modulator by two. In a variant from this basic scheme for realizing even-order N.sup.th -order sigma-delta modulators, an additional integrator with feedback applied from output to input may be included with the second-order resonator or cascade of them, thereby to obtain an odd-order N.sup.th -order sigma-delta modulator.
My allowed U.S. patent application Ser. No. 608,076 filed Nov. 1, 1990, entitled "PLURAL-ORDER SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTERS USING BOTH SINGLE-BIT AND MULTIPLE-BIT QUANTIZERS" and assigned to General Electric Company is incorporated herein by reference. U.S. patent application Ser. No. 608,076 describes a first-order sigma-delta modulator that has a single feedback loop including a linear network and a quantizer, which quantizer comprises a plural-bit (P-bit) ADC, a digital comparator and a single-bit DAC. The linear network comprises a subtractor, for differentially combining an analog feedback signal with an analog input signal to generate an error signal, and an integrator, for integrating the error signal to supply input signal to the quantizer. The loop behaves much the same as a conventional single-feedback-loop, one-bit sigma-delta modulator, inasfar as the feedback signal is concerned; but the P-bit output is available, so the truncation error can be determined. The truncation error is cancelled from the final output signal of this first-order sigma-delta modulator using a modicum of further digital circuitry.